WaveRunner 610Zi 美国力科WaveRunner示波器 WaveRunner 610Zi
- 型号：WaveRunner 610Zi
- 产地：山东 济南市
- 供应商：济南金力通电子设备有限公司
- 供应商报价： 电议
- 标签：美国力科WaveRunner示波器 WaveRunner 610Zi,美国力科WaveRunner示波器 WaveRunner 610Zi价格,美国力科WaveRunner示波器 WaveRunner 610Zi厂家
产品库
| 类型 | 数字示波器 | 品Pai | 美国力科 |
| 型号 | WaveRunner 610Zi | 通道数 | 4 |
| 带宽 | 1G（MHz） | 采样率 | 见参数（GS/s） |
| 记录长度 | 见参数（k） | 是否提供加工定制 | 否 |
| Vertical System | |
| Nominal Analog Bandwidth @ Ω 50 10 mV-1 V/div | 1 GHz (≥2 mV/div) |
| Rise Time (20¨C80%) | 280 ps (typical) |
| Rise Time (10¨C90%) | 375 ps (typical) |
| Input Channels | 4 |
| Bandwidth Limiters | 20MHz, 200MHz |
| Input Impedance | 50 Ω±2% or 1 MΩ||17pF, 10 MΩ || 9.5 pF with supplied Probe |
| Maximum Input Voltage | 50 Ω: 5V RMS ± 10V peak 1 MΩ: 400 V max. (DC + peak AC < 10 kHz) |
| Channel-Channel Isolation | > 100:1 up to rated BW |
| Vertical Resolution | 8 bits; up to 11 bits with enhanced resolution (ERES) |
| Sensitivity | 50 Ω:1 mV/div - 1 V/div, fully variable 1 MΩ: 1 mV/div - 10 V/div, fully variable |
| DC Vertical Gain Accuracy (Gain Component of DC Accuracy) | ±1% F.S. (typical), offset at 0V; ±1.5% F.S. (test limit), offset at 0V |
| Offset Range | 50 Ω: ±1.6 V @ 2 mV - 4.95 mV ±4 V @ 5mV - 9.9 mV ±8 V @ 10mV - 19.8 mV ±10 V @ 20mV - 1V 1 MΩ: ±1.6 V @ 2 mV - 4.95 mV ±4 V @ 5mV - 9.9 mV ±8 V @ 10mV - 19.8 mV ±16 V @ 20mV - 140 mV ±80 V @ 142mV - 1.4 V ±160 V @ 1.42mV - 10V |
| DC Vertical Offset Accuracy | ±(1.5% of offset setting +1% of full scale + 1 mV) (test limit) |
| Horizontal System | |
| Clock Accuracy | ≤1.5 ppm +(aging of 0.5 ppm/yr from last calibration) |
| Trigger and Interpolator Jitter | ≤ 3.5 psrms(typical) <0.1 psrms(typical, software assisted) |
| External Clock | DC to 100 MHz; (50 Ω/1 MΩ), EXT BNC input, Minimum rise time and amplitude requirements apply at low frequencies. |
| Acquisition System | |
| Single-Shot Sample Rate/Ch | 10 GS/s on 4Ch 20 GS/s on 2 Ch |
| Memory Options (4 Ch / 2 Ch / 1Ch) | S-32 Option: 32M / 64M / 64M (15,000) M-64 Option: 64M / 128M / 128M (15,000) |
| Standard Memory (4 Ch / 2 Ch / 1Ch) (Number of Segments) | 16 M / 32 M / 32M (4,500) |
| Acquisition Processing | |
| Enhanced Resolution (ERES) | From 8.5 to 11 bits vertical resolution |
| Triggering System | |
| Trigger Sensitivity with Edge Trigger (Ch 1¨C4) ProBus Inputs | 2 div @ < 1 GHz 1.5 div @< 500 MHz 1 div @ < 200 MHz 0.9 div @<10 MHz (DC, AC, and LFRej coupling, ≥ 10 mV/div, 50 Ω) |
| External Trigger Sensitivity, (Edge Trigger) | 2 div @ 1 GHz 1.5 div @ < 500 MHz 1 div @ <200 MHz 0.9 div @<10 MHz (DC, AC, and LFRej coupling) |
| Max. Trigger Frequency, SMART Trigger | 1.0 GHz @ ≥ 10 mV/div (minimum triggerable width 750 ps) |
